Module Level Defect Simulation in Digital Circuits

A new method for parametric defect modelling is developed for calculating the conditions for activating physical defects in the modules (for example, in library components) of digital circuits. The method affords for the first time the possibility to handle the defects which increase the number of states in the circuit. By using the concept of functional faults, the new method of defect modelling by logic conditions is generalized for hierarchical fault simulation. A method is proposed to find the types of faults that may occur in a real circuit, to determine their probabilities, and to find the input test patterns that detect these faults. A new hierarchical defectoriented fault simulation method is presented. At the higher (module) level simulation we use the functional fault model, at the lower level the defect/fault relationships in the form of defect coverage table and conditional defect probabilities. Experimental data of the hierarchical defectoriented simulation for ISCAS’85 benchmarks are presented, which show that classical stuck-at fault based simulation and the test coverage calculation, based on counting defects without considering defect probabilities, may lead to considerable overestimation of results.